Arm China frames edge AI as a full-stack CPU, NPU, VPU and AIOS problem

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At WAIC 2026, Arm China shifted attention away from cloud-scale clusters and toward the other end of AI deployment: cameras, robots, industrial gateways, wearables and edge nodes. In these environments, the central question is not simply whether a model can run, but whether it can run within strict power, thermal, memory and latency budgets.

Key takeaways

• The CPU remains the control plane for edge AI. Arm China highlighted Arm Helium, a vector extension for Cortex-M processors designed to improve DSP and lightweight machine-learning workloads. Its in-house Star CPU line supports Helium from STAR-MC2 onward. The demonstrated “Star 300” platform combines a STAR CPU and Arm Ethos NPU on FPGA to validate face-detection style workloads, making it closer to a design and software verification vehicle than a finished device.
• NPU evaluation is moving beyond peak TOPS. The upcoming Zhouyi X3-Pro architecture is described as a unified software, instruction and interface layer with differentiated hardware underneath. The plan includes low-power, mid-range and more complex inference configurations, with emphasis on mixed precision, configurable memory hierarchy and flexible cluster combinations.
• Video processing is being redesigned for machines. Under the Linglong VPU roadmap, Arm China discussed Emei and the planned Wudang VPU, both involving content-aware encoding. The more forward-looking idea is task-aware encoding, where preprocessing networks, virtual encoders and downstream AI tasks are trained together so compression preserves information useful for tracking or action recognition, not only human-perceived image quality.
• AIOS targets the missing software layer. The open AIOS alliance aims to define components such as a model engine, Agent orchestration, memory engine and DataFlow engine. The goal is to manage model routing, multimodal streams, Zero Copy data movement and heterogeneous hardware scheduling across local and cloud resources.

Why it matters

The broader signal is that edge AI is entering a systems-engineering phase. A device may need a CPU for real-time control, an NPU for model inference, a VPU for efficient visual data handling and an operating layer for orchestration, memory and security. If any one layer is inefficient, headline accelerator performance may not translate into product performance.

However, this is still largely a roadmap. Star 300 is a validation platform, Zhouyi X3-Pro lacks full public specifications, Wudang VPU is planned for a future release, and AIOS remains an early ecosystem effort. The real test will be whether these ideas become manufacturable chips, stable SDKs and a developer workflow that can survive long product lifecycles at the edge.

Source: InfoQ 中文